1. Field of the Invention
The present invention relates to an information processing system in which at least part of processing by application programs can be performed with reconfigurable programmable logic circuits. Also, the present invention relates to a circuit information management method and a circuit information storage device well-suited to the information processing system.
2. Description of the Prior Art
In the field of digital circuit elements, particularly application specific integrated circuits (ASIC), in order to reduce the development term of products, programmable logic circuits are widely used which comprise field programmable gate arrays (FPGA), programmable logic devices (PLD), and the like.
These programmable logic circuits, by loading circuit information describing logic circuits into them, permit the connections between internal logic circuits to be freely formed. Accordingly, the use of programmable logic circuits has the merit of eliminating the time for manufacturing integrated circuits, which has conventionally required from several weeks to several months after the end of circuit design. Particularly, as described in U.S. Pat. No. 4,700,187, electrically reconfigurable programmable logic circuits have the advantage of being able to be changed freely any number of times after once manufactured, so that they are being used more and more widely.
One example of a device for designing this type of programmable logic circuit is described in a patent specification entitled xe2x80x9cDevice and Method for Designing FPGA Circuitsxe2x80x9d (Japanese Published Unexamined Patent Application No. Hei 6-232259). This example, as a prior art example 1, will be described with reference to FIGS. 28 and 29.
FIG. 28 shows the configuration of a CAD system to design a large-sized FPGA circuit. This device has a database 12 in which a plurality of hard macro cells comprising FPGA function modules containing layout and wiring information and logic function information are cataloged, and designs a larger-sized FPGA integrated circuit by using the plurality of hard macro cells cataloged in the database for layout and wirings.
In this device, a designer operates a data input-output device 10 as a man-machine interface to run a file management program group 11. The file management program group 11 includes a logic file management program, a library management program, a layout and wiring management program, and the like to manage the database 12.
The database 12 comprises a logic file in which a plurality of pieces of FPGA logic function information are stored, a cell library in which FPGA cells as function modules are cataloged, and a layout and wiring file in which layout and wiring information internal to and external to FPGA is stored. In the cell library, multiple hard macro cells are cataloged which in advance have layout and wiring information and logic function information and execute specific functions as peripheral circuits and the like. The contents of each file of the database 12 are read for diagnosis from a diagnostic system 13 as required, and the diagnostic data 14 is outputted.
By sequentially using a drawing input system, a net list generation system, a layout system, an in-cell layout and wiring system, and an output program according to the contents of the files stored in the database, design drawings and a program for implementing a large-sized FPGA circuit are outputted.
FIG. 29 shows an example of the configuration of one-chip FPGA-based microcomputer system designed by the CAD system. The FPGA chip 20 comprises a CPU 21, a ROM 22, a RAM 23, an I/O port 24, a PIT (Programmable Interval Timer) 25 to measure an elapsed time of a program to be processed, a PIC (Programmable Interrupt Controller) 26 to control concurrent interrupt signals from a plurality of devices, and a DMAC (Direct Memory Access Controller) 27 to arbitrate necessary memory accesses with the CPU 21, each of which is connected to an address/data bus 28 and a control signal line 29.
Of these components, hard macro cells corresponding to the I/O port 24, PIT 25, PIC 26, and DMAC 27 are cataloged in advance in the cell library of the database 12 and, by simply reading the hard macro cells as they are and mapping them onto the FPGA chip 20, the hard macro cells can be laid out within the FPGA cells.
In the way described above, according to the prior art example 1, by using a library in which a plurality of hard macro cells comprising FPGA function modules having layout and wiring information and logic function information in advance are cataloged, and making layout and wirings using the plurality of hard macro cells cataloged in the library, a less heavily loaded system design can be made within a shortened development term, taking advantage of existing FPGA circuits as intellectual property.
Although the prior art example 1 described above relates to invention on the designing of one FPGA chip, recent logic circuits are increasing in complexity and their circuit scale has become large to such an extent that it cannot be achieved by one programmable logic circuit device.
As one method for solving this problem, a method is proposed which re-forms programmable logic circuits in the middle of processing to implement different logic circuits at different times. This method is advantageous in that various processing can be performed relatively quickly even in portable information terminals or the like, which are limited in the size of internal circuits because of their compact size.
However, one disadvantage of this method is that a programmable logic circuit requires much time to re-form because circuit information of the entire circuit should be read again. Moreover, re-forming in the middle of processing requires extra processing, that is, temporarily stopping processing, saving data at that time to a storage external to the programmable logic circuit, reading new circuit information for the re-forming, and inputting the data before the re-forming and new data for the re-forming. Input and output of data is redundant.
To solve this problem, a programmable logic circuit described in a data book entitled xe2x80x9cCONFIGURABLE LOGICxe2x80x9d published by Atmel Corporation, a U.S. company and a programmable logic circuit described in a data book entitled xe2x80x9cTHE PROGRAMMABLE LOGICxe2x80x9d published by Xilinx, Inc., a U.S. company have a data storage for storing data and are partially re-formed by reading part of circuit information from the external storage even during operation of the circuits, thereby minimizing the time required for re-forming.
A problem with the use of such a programmable logic circuit in an information processing system is that re-forming into a desired logic circuit must be performed quickly and efficiently by retrieving circuit information for forming the desired logic circuit from a storing destination and synthesizing a plurality of pieces of circuit information, as required, to a format suitable for processing.
An information system that re-forms the above-described plurality of pieces of circuit information into a programmable logic circuit at different times and performs predetermined processing can be connected to a network for use. An example of this is a xe2x80x9creconfigurable network computerxe2x80x9d described in Japanese Published Unexamined Patent Application No. Hei 10-78932, which will be described below as a prior art example 2 with reference to FIG. 30.
An information processing system of the prior art example 2 comprises a plurality of computers connected to a communication network NET, at least one of which is a computer (application server) SB that distributes an application program and the remainder are client computers CL that down-load and execute the application program. Extended hardware (extended HW) 31 that can be functionally changed as required by a program and be re-formed is installed in part of the plurality of client computers CL.
The application program AP stored in the server SB, for part of functions thereof, contains program codes (extended codes) of the extended hardware and codes of the main processor (main P) 32 of a client computer CL.
The OS of a client computer CL has a function to judge whether the extended hardware 31 is installed, and if it is installed, has a code selection function 33 to retrieve only codes suitable for the hardware configuration from the application program AP, like the upper client computer CL in FIG. 30. Like the lower client computer CL in FIG. 30, if the extended hardware 31 is not installed, the codes of the main processor 32 are selected by the code selection function 33 so that the application can be used.
In another configuration, functions implemented by the extended hardware 31 are implemented as OS extended functions or dynamic libraries that can be dynamically added and deleted later onto a client computer CL, and the application program AP registers the type of extended functions or dynamic libraries used in the process of processing to the OS. The OS uses extended functions or dynamic libraries on the client, if any, and otherwise, transfers required extended functions or dynamic libraries from the server SB on the network NET to use them.
Codes for the main processor 32 and codes for the extended hardware 31 are not united, but different codes may be provided on a host computer, for each of application programs AP, OS extended functions, or dynamic libraries.
Furthermore, in the case of the prior art example 2, when the configurations of programmable logic circuits comprising the extended hardware are different among clients, the extended codes may be replaced by codes representing basic modules that describe the functions of logic circuits comprising proper numbers of gates and input-output pins by Boolean expressions and the like, and connection relationships among them. The basic modules can be referenced by other circuits for reuse as intellectual property.
Furthermore, the server or clients are provided with a function to allocate the basic modules respectively to the basic programs of programmable logic circuits, and a function, when an extended code is large enough to extend to a plurality of programmable logic circuit chips, to split the basic modules according to the degree of connections before laying them out on each programmable logic circuit chip.
Also, a hardware resource management function and a code interchange function are provided. The former reuses disused hardware resources for other application programs so that a plurality of applications using the extended hardware can be executed concurrently, and the latter interchanges extended codes not fitting within the extended hardware in time sharing mode.
There is also provided an extended hardware management function that performs selection for a plurality of application programs not fitting within hardware resources, based on a priority value set for each application program executed on a client, the processing capability value of a main processor, the processing capability value of extended hardware, the amount of hardware resource, and a processing capability value required for code interchange.
When a plurality of applications use an identical extended code at the same time in the extended hardware, only internal states are switched in time sharing mode and functions are shared.
As has been described above, in the case of the prior art example 2, when the application program distributed from the server is executed on a computer connected over the network at a client, the client is provided with extended hardware that is functionally changed as required by a program and is reconfigurable, the application program stored in the server is made to contain main processor codes of the client and extended codes, the configuration of the client computer is changed to suit processing by the code selection function to determine the existence and type of the extended hardware, whereby the application program can be executed quickly.
In an attempt to start new service requiring clients to have special hardware, conventionally, users at the clients have been required to install new hardware for this purpose and the service provider has offered the new service only to limited users having the new hardware. However, by implementing the above-mentioned prior art example 2, the new service can be started without installing the new hardware.
As has been described above, use of the FPGA circuit design device and method of the prior art example 1 would allow FPGA circuits designed previously to be reused as hard macro cells but require the task of combining the hard macro cells to produce circuits that actually function.
To combine the hard macro cells, in the case of the prior art example 1, while viewing data 14 of diagnostic results in the diagnostic system 13, a circuit designer references FPGA cells including hard macro cells cataloged in the cell library of the database and inputs a circuit drawing in the drawing input system. A net list is generated from the inputted circuit drawings in the net list generation system, and according to the generated net list, hard macro cells are laid out in the layout system, and wirings among the hard macro cells are made in the in-cell layout and wiring system.
For this reason, reusing hard macro cells to design one circuit would contribute to reduction in a design term in comparison with the case of designing all circuits. However, there is still a problem that computational complexity and time for laying out and connecting hard macro cells are required.
Also, the designer must input circuit drawings while referencing hard macro cells cataloged in the cell library. Furthermore, there is a problem that a system becomes large, because of the need for a system that generates a net list from inputted circuit drawings, a layout system that lays out hard macro cells, and an in-cell layout and wiring system that connects hard macro cells.
In other words, the prior art example 1 is useful for efficiently designing an FPGA chip having a high integration level by using hard macro cells designed previously to design a specific circuit without constraints of time, as in the case of designing circuits formed on an ASIC, for example, whereas, for example, in an attempt to perform processing of part of an application program by programmable logic circuits instead of software processing, this technique is unsuitable for creation of information of circuits to be formed in the programmable logic circuits.
On the other hand, if a network computer device of the prior art example 2 is used, by using extended codes passed from a server SB, processing of part of an application program can be performed by hardware without installing new hardware, so that rapid processing of the application program by hardware becomes possible.
At this time, in the prior art example 2, circuit information of circuits formed in programmable logic circuits such as extended hardware must be stored, for each circuit, before an application program is executed, as extended codes in the application program, OS extended functions, or dynamic libraries added to the program during execution.
For this reason, each of client computers must have a storage unit to store circuit information of circuits formed in programmable logic circuits even when it does not have extended hardware.
In the case of the prior art example 2, one circuit may be comprised of a collection of basic modules having smaller functions. The basic modules, which are available for reference from other circuits, can be reused as intellectual property.
However, one problem is that, as described above, if a client computer is provided with circuit information stored as extended codes, which is comprised of a collection of basic modules, when one of the basic modules must be modified or improved, the whole of the circuit Ad information stored in the client computer must be re-created from the beginning.
An object of the present invention is to offer an information processing system that processes at least part of an application program with programmable logic circuits, wherein the information processing system need not have circuit information of the programmable logic circuits in advance.
Another object of the present invention is to significantly reduce computational complexity for combining circuit information for layout and wirings although circuit information designed previously is reused.
Still another object of the present invention is to enable a highly flexible re-forming of circuit information for forming circuits in the event of modifications and improvements of the circuit information so that an application program using circuits formed in programmable logic circuits can perform processing, without the need to create the circuit information, for example, by combining a plurality of basic modules, before the application program is started.
To solve the above-mentioned problems, an information processing system according to a first invention that performs at least part of processing of an application program with programmable logic circuits, comprises:
a processing part that includes the programmable logic circuits and performs processing using circuits formed in the programmable logic circuits by instructions from the application program;
a memory part that stores a plurality of pieces of circuit information for forming the circuits in the programmable logic circuits;
an editing part that includes a function to generate circuit information of one circuit specified by specification information by using the plurality of pieces of circuit information stored in the memory part; and
an acquisition part that, to identify a circuit to be formed in the programmable logic circuits, passes information specified by the application program, as the specification information, to the editing part, obtains circuit information of the circuit specified by the specification information wherein the circuit information arrives from the editing part, and forms the specified circuit in the programmable logic circuits of the processing part by the circuit information.
An information processing system of a second invention is characterized in the first invention in that:
a portion constituting the memory part, a portion constituting the editing part, and a portion constituting the acquisition part and the processing part are connected over a network.
An information processing system of a third invention is characterized in the first or second invention in that:
each of the plurality of pieces of circuit information stored in the memory part has an identifier of its own circuit information, and in the case where part or all of the circuit information is formed with other circuit information, has the identifiers of the other circuit information as reference identifiers, as circuit data for forming circuits in the programmable logic circuits; and
the editing part generates circuit information of a circuit specified by the specification information passed from the acquisition part by obtaining the circuit information of the specified circuit and the other circuit information indicated by the reference identifier from the memory part.
An information processing system of a fourth invention is characterized in the third invention in that:
the editing part, in response to the specification information from the acquisition part, inquires of the memory part about circuit information of a circuit specified by the specification information by an identifier thereof;
the memory part, in response to the inquiry from the editing part, if circuit information indicated by the identifier at the inquiry contains a reference identifier, returns the reference identifier to the editing part; and
the editing part uses the reference identifier obtained from the memory part to obtain the other circuit information indicated by the reference identifier from the memory part.
An information processing system of a fifth invention is characterized in the first or second invention in that:
each of the plurality of pieces of circuit information stored in the memory part comprises a circuit data unit and an additional information unit thereof;
the additional information unit contains an identifier of its own circuit information, and in the case where part or all of the circuit information is formed with other circuit information, contains the identifiers of the other circuit information as reference identifiers;
the circuit data unit is for forming circuits in the programmable logic circuits, and in the case where part or all of the circuit information is formed with other circuit information, circuit data of the part or all of the circuit information is described using the reference identifiers;
the editing part, in response to the specification information from the acquisition part, inquires of the memory part about circuit information of a circuit specified by the specification information by an identifier thereof;
the memory part, in response to the inquiry from the editing part, if the additional information unit of circuit information indicated by the identifier at the inquiry contains a reference identifier, returns the reference identifier to the editing part; and
the editing part uses the reference identifier obtained from the memory part to obtain the other circuit information indicated by the reference identifier from the memory part.
An information processing system of a sixth invention is characterized in the fifth invention in that:
the circuit data unit of the circuit information stored in the memory part is described by pairs of the address of a configuration memory of the programmable logic circuits and circuit data stored in the address; and
in the case where part or all of the circuit information is formed with other circuit information, the reference identifiers are described as circuit data of addresses corresponding to positions where the other circuit information is referenced in the circuit information.
An information processing system of a seventh invention is characterized in the sixth invention in that:
the editing part links the other circuit information corresponding to the reference identifier to circuit information in which the reference identifier is contained, in such a way that the address at which the reference identifier is described as circuit data of circuit information of a circuit specified by the specification information is added to all the addresses of the circuit data unit of the other circuit information corresponding to the reference identifier.
[Action]
In an information processing system of the first invention, during execution of an application program, in order to have the application program perform processing with programmable logic circuits of the processing part, information for identifying a circuit to be formed in the programmable logic circuits is sent to the acquisition part. The acquisition part passes the information to the editing part as specification information of circuit information. The editing part sends the specification information to the memory part.
The memory part returns circuit information specified in the specification information to the editing part. The editing part receives it, and if other circuit information in the memory part is also required to generate specified circuit information, obtains the other circuit information from the memory part. The editing part generates specified circuit information from a plurality of pieces of circuit information obtained from the memory part and returns it to the acquisition part as information requested by the specification information. The acquisition part re-forms the circuit information obtained from the editing part in the programmable logic circuits of the processing part.
The processing part can perform processing designated by the application program by using the circuits re-formed in the programmable logic circuits.
As has been described above, in the information processing system of the first invention, if specification information is passed to the acquisition part during execution of an application program, in response to requests from the acquisition part, the editing part automatically generates circuit information to be formed on programmable logic circuits of the processing part and returns it to the acquisition part, and the acquisition part re-forms the circuit information in the programmable logic circuits, so circuit information need not be stored in advance within an application program or the like.
In the information processing system of the second invention, a portion constituting the memory part, a portion constituting the editing part, and a portion constituting the acquisition part and the processing part are connected over a network, so that the editing part and the memory part need not be provided within one information processing apparatus. Accordingly, to the acquisition part, the processing part, and the application processing apparatus operating with application programs, the system appears to be constructed so that, if specification information is sent over a network, circuit information corresponding to the specification information is automatically sent; the memory part, the editing part, and the acquisition part and processing part can be freely organized.
In the information processing system of the third invention, circuit information stored in the memory part has a so-called tree structure, with circuit information consisting of circuit data not referencing other circuits at the lowest layer.
That is, each piece of circuit information has, e.g., a circuit name as its own identifier. Each piece of the circuit information, when part or all thereof is formed with other circuit information, has, as circuit data, the identifiers of the other circuit information as reference identifiers. As the reference identifiers, the circuit names of the other circuit information may be used. The other circuit information indicated by the reference identifiers can also be partially or wholly formed with other circuit information. Circuit information at the lowest layer contains no reference identifier in the circuit data.
The editing part, when part of circuit information specified in specification information is formed with other circuit information, obtains the specified circuit information and other circuit information indicated by a reference identifier contained in it from the memory part and links them, and generates the specified circuit information. If all of the specified circuit information is formed with other circuit information, the editing part obtains all pieces of other circuit information indicated by reference identifiers from the memory part to link them and generates the specified circuit information.
In this case, the editing part obtains a reference identifier of specified circuit information from the memory part or from specified circuit information, obtained from the memory part. In the case of the third invention, either of them is possible.
A fourth invention relates to a method for the editing part to obtain a reference identifier of specified circuit information. In the fourth invention, the editing part makes an inquiry about circuit information to the memory part by an identifier of circuit information indicated by specification information passed from the acquisition part. On receiving the identifier of circuit information from the editing part, the memory part returns the circuit information to the editing part, and if the circuit information indicated by the identifier contains a reference identifier, returns the reference identifier to the editing part.
The editing part sends the received reference identifier to the memory part again. The memory part returns circuit information indicated by the reference identifier to the editing part, and if the circuit information further contains a reference identifier, returns the reference identifier to the editing part.
On further receiving a reference identifier, the editing part repeats the above operations and obtains from the memory part all circuit information necessary to generate circuit information of a specified circuit.
The fifth invention relates to a data structure of circuit information stored in the memory part. Use of the data structure allows quick exchange of an identifier of the circuit information and the circuit information between the editing part and the memory part.
In other words, circuit information comprises a circuit data unit and an additional information unit thereof. The additional information unit contains an identifier of its own circuit information, and in the case where part or all of the circuit information is formed with other circuit information, contains an identifiers of the other circuit information as reference identifiers. The circuit data unit is for forming circuits in the programmable logic circuits, and in the case where part or all of the circuit information is formed with other circuit information, circuit data of the part or all of the circuit information is described using the reference identifiers.
In response to an inquiry by an identifier of circuit information from the editing part, the memory part returns to the editing part a reference identifier contained in the additional information unit of circuit information indicated by the identifier. The editing part sends the reference identifier obtained from the memory part to the memory part to make an inquiry about circuit information again, and obtains from the memory part circuit information indicated by the reference identifier.
According to the fifth invention, the editing part need not analyze circuit information to find out a reference identifier of other circuit information forming specified circuit information and can therefore quickly obtain necessary circuit information from the memory part.
According to the sixth invention, the circuit data unit of circuit information is described by pairs of the address of a configuration memory of programmable logic circuits and circuit data stored in the address, and in the case where part or all of the circuit information is formed with other circuit information, the reference identifiers are described as circuit data of addresses corresponding to positions where the other circuit information is referenced in the circuit information.
Accordingly, the editing part, by allocating circuit information indicated by the reference identifier according to data contents of the circuit data unit, can quickly assemble circuit information of a circuit specified by specification information.
The seventh invention relates to a concrete method for linking circuit information indicated by a reference identifier in the editing part to circuit information indicated by specification information. According to the seventh invention, the address at which a reference identifier of the circuit data unit of circuit information is contained is added to all the addresses of the circuit data unit of other circuit information corresponding to the reference identifier to link the other circuit information to the circuit information in which the reference identifier is contained.
As described above, according to the seventh invention, simply by adding offset to addresses, circuit information indicated by a reference identifier can be linked to circuit information in which the reference identifier is contained, so that little time is required for computations on layout and wirings. Therefore, the editing part can generate circuit information in a short time.